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• Redesign

  Bud Bennett • 4 天前 • 0 comments

  The 100MHz Probe:

  When I decided to add the 10MHz and 1MHz versions I had to tweak the 100MHz probe a bit. All of the versions use the same PCB layout. The higher supply voltage on the slower versions forced me to change the larger tank bypass capacitors from 0402 size to 0603 because it is difficult to get large 0402 ceramic caps rated above 16V. Also, the input resistor string was changed from 3x3.3Meg + 62k to 4x2.49Meg using 0805 resistors (see reason below).

  The 10MHz Probe:

  Technically, not a redesign but constrained by keeping the same PCB layout as the 100MHz probe. It was difficult to find suitable opamps. They had to meet the following criteria:

  1. A dual opamp in a MSOP8 (or VSSOP8) with the same pinout as the LTC6269-10, and a single opamp in a SOT26 or SOT25 with the same pinout as the LTC6268.
  2. Supply voltage > 12V (More supply voltage yields a higher differential input signal)
  3. Gain-BW product > 20MHz - 60MHz, depending upon how gain was allocated to the first and second stages.
  4. Slew Rate > 400V/µs. (6Vpeak x 10MHz x 2π)
  5. pA input bias current (for low noise)
  6. Rail-to-rail output swing would be nice.
  7. Less expensive than the LTC6268/9 (this is not difficult).

  Needless to say this narrowed the field a bit. After loosening a few of the criteria I finally settled on the OPA2810 and OPA810, which has the following specs:

  1. Available in a VSSOP and SOT25 package.
  2. Max supply voltage 24V
  3. GBW = 70MHz
  4. Slew Rate = 192V/µs
  5. 2pA input bias current typical
  6. Rail-to-rail in/out.
  7. Less than $5.00 for the OPA2810, and around $3.50 for the OPA810.

  I settled on a 15V supply voltage, which would yield an output swing of 14Vpp with the rail-rail output. Since the gain is set at 1/10 V/V the differential input voltage swing is set at 140Vpp. The higher supply voltage also means that less input attenuation would be required and still meet the common mode range needed, so I decreased the attenuation from 1/250 V/V to 1/100V/V. 

  I also thought, mistakenly, that reducing the resistance of the attenuator from 10MegΩ to 5MegΩ would reduce the Johnson thermal noise. This increased the input capacitors from 10pF to 20pF to keep the same crossover frequency.

  With a GBW of 70MHz the OPA2810 won't have a -3dB BW with a gain above 5 or 6. I set the gain at 5, which makes the second stage gain an easy 2. You want to have the first gain stage as high as possible to suppress input referred noise from the later stages. You also want to have the last stage set the bandwidth of the probe. The max CM voltage x attenuation + max single-ended input voltage x attenuation x first stage gain must be less than 7.25V:  353V/100 + 70V/100 * 3 = 5.63V. The gain of 3 (instead of 5) is because the input is single-ended and has a common mode component to it. If the input signal was differential the max output swing drops to 5.28V.

  I had to give up having full bandwidth with a 70Vpeak input swing. The slew rate of the last stage will only allow a 3Vpeak sinusoid without hitting the slew rate limit.

  The datasheet suggests keeping the feedback resistors below 2k to avoid degrading the noise performance of the opamp. The max power dissipation of an 0603 resistor is usually less than 0.1W. A quick check on the feedback resistor max dissipation in the second stage = 10.9mW, no problem there. A fat finger check of the total power dissipation of the probe -- 4mA x 3ma/opamp + 3mA (for LED + rail splitter) is less than 250mW. It should be pretty cool.

  The bypass caps were changed in accordance with those suggested by the datasheet. This forced a change to the large 2.2μF and 4.7μF capacitors -- changing the footprint to 0603 to make it easier to get them rated for 25V or 35V. (And this in turn caused the update to the 100MHz PCB layout.)

  uh..oh...

  At this point I found an error in the design of the old diff probe. When I was searching for parts on Digikey and JLCPCB I noticed that all of the 0603 resistors had a max working...

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• First Pass Evaluation

  Bud Bennett • 07/08/2025 at 21:30 • 0 comments

  It's 2025-07-08. I received the core probe PCB, the generic micro USB DB and the buck converter DB. They all work, but I will need to make changes on the daughter boards to prevent problems when stacking onto the core probe.

  The Probe Evaluation:

  I did not take rigorous data this time. The probe performed as expected, with a few problems that were easily resolved. I had a couple of issues during assembly. I did not have the 412Ω or 3.92k resistors in my inventory. Luckily, I measured two 3.9k 1% resistors to be 3918Ω and stacked two 820Ω resistors on top of each other to get 411Ω. I did not have the 620mΩ snubber resistors either, so 1Ω would have to do.

  When I powered it up it drew 25ma or 60mA randomly as I fiddled with the board. Clearly there was an intermittent connection somewhere -- it turned out to be the power pin of the LTC6269-10. A bit of work with the hot air rework station fixed that. I now draws 60mA and I get a signal out when a signal is applied to the input.

  Then I noticed that there was a difference of a few hundred mV between the positive and negative supply rails. The rail splitter opamp was oscillating (a sawtooth waveform) at 10kHz. I disconnected the 10uF cap at the output of U4 to no effect. Then I replaced the FB3 ferrite bead with a 3 Ohm resistor and the oscillation went away. Lesson learned. The small resistor is 10X the resistance of the bead, but there is not much current flowing through it -- even at full scale output voltage swing the effect on the GND voltage will be just a few hundred uV.

  After a quick check to see if the gain was correct I calibrated the DC common mode and the two AC gain paths without any issues. It did not require any change in the large attenuator capacitors, or any additional capacitor in the open 0603 capacitor location. I had calculated those values based upon the -7.5% change on the 10pF input capacitors and it proved correct this time as well. It also helped to have a 15.5pF trim range.

  I was able to trim the output offset to less than 1mV, using a DVM. This offset moves several mV as the supply voltage changes a few hundred mV. I would not recommend swapping DC-DC adapters, that will have different voltages, if you are going to implement the offset adjust feature. But using a daughter board with a regulator should be fine.

  Overall DC gain was a smidge high -- about 1%, which I attributed to my stacked 820Ω parallel kluge. I can't measure AC gain much past 10MHz, but it was good to that point. I applied 20Vpp (the max of my function generator) and did not see any clipping at the output.

  The noisy output is still there. I can see about 100mVpp of hash at the output when the scope is set to 10X mode.

  In short, this probe looks nearly identical to the old one. That's good!

  The Buck Converter Daughter Board:

  l built two versions of the buck converter -- one with an RT8259 chip and another with an RY8310 chip. They are nearly identical performers. Digikey sells the RT8259 for more than $1.5, while LCSC sells the RY8310 for around $0.10. There is a side benefit to the RY8310 in that it doesn't require a freewheeling Schottky diode at the switch node. 

  Both boards worked well. They both were almost exactly 5.3V at the output. There was a 20mVpp 1.4/1.5MHz square wave ripple at the output, as expected. The load and line regulation was excellent -- about 2-mV change for 50mA change in load current, and about the same 2mV change as the input voltage changed from 9-12.5V. The overhead was also very good as both converters would not drop the output voltage until input voltage was below 6V.

  The RY8310 was more efficient -- 80% @12V, 85% @9V. The RT8259 was about 5% lower. Still not bad. At this low current (60mA) both boards remained cool, as they should because they only dissipated around 150mW.

  Pairing the buck converter DB with the probe:

  I tried to mount the RT8259 daughter board under the probe and immediately...

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• The Bane of Mutual Inductance

  Bud Bennett • 06/23/2025 at 19:16 • 0 comments

  I've been simulating the daughter board voltage regulators lately. It seems like the data sheets for these LDO regulators, and the switchers too, don't account for any inductance in the power input leads. That's not the case here. I expect almost all users (except maybe some that employ batteries for power) are going to have relatively long -- around 1 meter -- leads running from the power adapter. This creates both lead inductance and mutual inductance between the leads if they are close together.

  The lead inductance depends upon the diameter of the wire and its length. The mutual inductance depends upon the distance between the two wires. All of this can be modeled in SPICE. 

  It is not too difficult to create a model for the input power leads that depends upon the wire's AWG and length. The coupling between the wires depends upon their separation, which is pretty small for these thin wires, and therefore K is at the high end of the range (between 0.7 and 0.9) I believe. The interesting thing to note is that the higher/thinner AWG tends to have a higher inductance, but also a higher resistance that tends to lower the Q of the tuned circuit. For example, a 1m long 26AWG wire has an self inductance of 1.68µH and R=128mΩ, where the same length of 30AWG has a self inductance of 1.78µH and R=327mΩ.

  I first discovered this when I simulated the LP2951 LDO. The data sheet shows a pretty basic application:

  A minimal input bypass cap and 2.2uF for the output. And this is what the data sheet has to say about bypassing:

  A bypass capacitor is recommended across the
  LP2950/LP2951 input to ground if more than 4 inches of
  wire connects the input to either a battery or power supply
  filter capacitor.
  Input capacitance at the LP2951 Feedback Pin 7 can
  create a pole, causing instability if high value external
  resistors are used to set the output voltage. Adding a 100 pF
  capacitor between the Output Pin 1 and the Feedback Pin 7
  and increasing the output filter capacitor to at least 3.3 F
  will stabilize the feedback loop.

  So this is the simulation result when I used the suggested values for ceramic capacitors, 1uF at input and 3.3uF at output, and set the length of the input leads to 125mm (~5in) and AWG=28: (load current is 50mA)

  That doesn't look too good. The data sheet specifically states that low ESR bypass caps can be used. This is presented in a plot:

  If I set the length of the input leads to 1m the oscillation disappears for steady state (due to the lower Q), but still looks pretty ringy dingy when excited:

  In order to kill any possibility of oscillation a 1Ω snubber resistor should be added to the input capacitor. Then things look pretty good, even when driving the inductive looking load of the slim probe.

  That underdamped response is due to the ferrite bead inductance and doesn't go away with increased snubber resistance. There apparently is no need for any large ESR output capacitor, but I will keep a discrete resistor in series with the output capacitor just in case.

  Mutual Inductance Effects on the Buck Converter Daughter Board Design:

  After all of that prior discussion, I won't bore with the details here. The problem I have is that I was not able to simulate the buck converter (off-brand manufacturer with limited modeling resources) and released the design without adding any discrete snubber resistors. 

  I fudged a simulation by using a similar switching converter IC model that ADI had a model for: the LT1616. As expected, the buck converter did not like the inductance of the input leads either. But it appears that the snubber resistors might not be necessary. The only way to tell is to build it and test it. 

  I put the lead inductance model in series with the buck converter input and checked in over various simulation parameters. There is one interesting phenomenon that show up: if you connect a powered adapter to the daughter board there's a chance that you...

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• Daughter Board Variety

  Bud Bennett • 06/21/2025 at 21:03 • 0 comments

  There are plans for 5 daughter board variants:

  1. Generic microUSB interface. 5V in, 5V out.
  2. Discrete voltage regulator (see previous log.) 7.5 - 12V in, 5.3V out.
  3. SOT89 LDO regulator. 7.5 - 12V in, 5.3V out.
  4. SOIC8 LDO regulator. 7.5 - 12Vin, 5.3V out.
  5. Switching regulator (buck converter). 7.5 - 12V in, 5.3V out.

  They all fit onto the 13x13mm daughterboard dimension. If none of these tickle your fancy, then make your own.

  Generic micro-USB:

  There's not much going on here. Just a standard micro USB (B-type) mounted on the edge of the daughter board as so:

  The 5V output connects to the probe power supply inputs through the header pins. The connector is an Amphenol 10103594-0001LF -- hopefully easy to get and not too expensive. This is probably what I will use for my slim probes since I have jiggered my wall adapters to output 5.25VDC.

  SOT89 LDO Daughter Board:

  This board uses the same LDO as what Paul used for his original probe. The LDO is an XC6216 adjustable voltage regulator IC, that comes in a SOT89-5 package.

  There are a few alternative LDO ICs that will work as well, if you can't get the XC6216. 

  The SOT89 should be able to handle the power dissipation easily.

  SOIC8 LDO Daughter Board:

  I used a widely available LP2951 voltage regulator that comes in a SOIC package option. It's a bit large, but it fits.

  There are three main manufacturers: TI, On semi, and Micro Chip. It is relatively inexpensive, around $0.50/each in low quantities.

  Buck Converter Daughter Board:

  I designed this board just for grins and giggles. It should be much lower power dissipation than the LDO alternatives. But it might be too noisy to be located so close to the probe circuitry. The switching regulator is a Richtek RT8259 (with RyChip RY8310 as a second source.) It switches at 1.2-1.4MHz, which allows for small components.

• VREG DB Survival

  Bud Bennett • 06/16/2025 at 20:52 • 1 comment

  I received an order of 5 USB-C trigger boards a couple of days ago. The available voltages from the trigger board are 9V, 12V, 15V and 20V. I have two bona fide USB-C adapter/chargers, both from Samsung, one is 25W and the other is 45W. I also have two clones of Apple adapters with USB-C jacks and a USB-C adapter for the Raspberry Pi 4.  The first thing I did was to plug a trigger board into the USB-C port of my desktop computer. The little blue LED on the trigger board did not light up and the voltage output read 5VDC. I expected this behavior.

  Then I connected the trigger board to the 45W adapter. The LED indicator lit immediately and the trigger board put 9VDC at the outputs. The problem with this is that the trigger board is set for 12V output. I'm a bit confused at this point so I plug the trigger board into the 25W adapter. The LED indicator eventually lights up after maybe 5-10 seconds. The output voltage is 12VDC. The two Apple clone adapters both light the LED immediately and put out 12.4VDC. The RPi adapter only puts out 5V. Now I'm really confused as to what is happening. 

  I trolled the internet as to what the issue could be but found nothing useful. At this point I have zero trust that the trigger board will output the correct voltage and it dawns on me that the circuit I designed probably won't survive in the wild without some improved robustness. The VREG daughter board must not fail or damage the expensive core probe circuitry if/when 20VDC is applied to its supply pins! 

  When I was designing circuits for a living I worked with some very experienced people (you might even call them legends.) They taught me a couple lessons:

  1. The best circuit designs are the ones that apply to the broadest range of applications.
  2. Sometimes a circuit's survival is more important than its performance.

  The PCB is tiny, only 13x13mm. It is also a DIY project, so 0201 components are out of consideration. I figure I could add a single SOT23 (not the difficult to solder SC70) and 2-3 resistors if most of the resistors could be 0402 size. After toiling away for a couple of hours on LTSpice I finally had a Eureka moment -- using another TL431/TL432 as a reference/comparator in the following circuit:

  This worked like a charm in LTSpice with behavioral models for the TL432. When the input voltage exceeds 13.2V the voltage at the REF pin of U2 exceeds 2.5V, and U2 will draw a lot of current from its cathode pin, effectively shutting down the output voltage at J3. U1 will attempt to compensate, but all it can do is reduce its current until it goes to zero. R4 is used to share the current through R1 and keep the power dissipation below the 100mW limit for 0603 resistors. This action saves Q1 and Q2 and R1 from burning up when 20V is applied. D1 protects the components against reverse polarity inputs.

  Then the gloom settled in as I realized that the behavioral models might not exhibit all of the correct behavior of the TL432. Here's the problem: Where is the current coming from to power U2? I measured pA of current into the anode of U2 using the first behavioral model from TI. The second SPICE model from TI sucked a whopping 1uA from the anode pin until it began to override U1. Still not correct.

  TI publishes the anode current vs voltage in its datasheet:

  That's not really helpful. Fortunately, TI published a schematic, with values, of the TL431 in the datasheet:

  And I created a schematic to imitate U2 in LTSpice:

  I used generic LTSpice NPN and PNP models which forced me to change R13 in order to get the circuit to regulate at 2.5V. Now I expected the currents at REF and K to be more realistic (but probably not perfect.) A DC sweep of V1 confirmed it:

  R18 monitors the current into the anode and R19 monitors the current into the REF pin. There's no contest...nearly all the current is going into the anode. This gives me some confidence that the over-voltage protection won't interfere with the normal...

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